for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim's website at www.maxim-ic.com. general description the max3202e/max3203e/max3204e/max3206e arelow-capacitance 15kv esd-protection diode arrays designed to protect sensitive electronics attached to communication lines. each channel consists of a pair of diodes that steer esd current pulses to v cc or gnd. the max3202e/max3203e/max3204e/max3206e pro-tect against esd pulses up to 15kv human body model, 8kv contact discharge, and 15kv air-gap discharge, as specified in iec 61000-4-2. these devices have a 5pf capacitance per channel, making them ideal for use on high-speed data i/o interfaces. the max3202e is a two-channel device intended for usb and usb 2.0 applications. the max3203e is a triple-esd structure intended for usb on-the-go (otg) and video applications. the max3204e is a quad-esd structure designed for ethernet and firewire ? applications, and the max3206e is a six-channel device designed forcell phone connectors and svga video connections. all devices are available in tiny 4-bump (1.05mm x 1.05mm) wlp, 6-bump (1.05mm x 1.57mm) wlp, 9-bump (1.52mm x 1.52mm) wlp, 6-pin (3mm x 3mm) tdfn, and 12-pin (4mm x 4mm) tqfn packages and are specified for -40c to +85c operation. applications usb video usb 2.0 cell phones ethernet svga video connections firewire features ? high-speed data line esd protection ?5kv?uman body model?kv?ec 61000-4-2, contact discharge ?5kv?ec 61000-4-2, air-gap discharge ? tiny wlp package available ? low 5pf input capacitance ? low 1na (max) leakage current ? low 1na supply current ? +0.9v to +5.5v supply voltage range ? 2-, 3-, 4-, or 6-channel devices available max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces ________________________________________________________________ maxim integrated products 1 ordering information 19-2739; rev 5; 6/11 * ep = exposed pad. note: all devices operate over -40c to +85c temperature range. + denotes a lead(pb)-free/rohs-compliant package. part pin-package top mark ma3202e ews+t 4 wlp +aa max3202eett+t 6 tdfn-ep* +adq ma3203e eewt+t 6 wlp +bg max3203eett+t 6 tdfn-ep* +ado ma3204e ewt+t 6 wlp +al max3204eett+t 6 tdfn-ep* +adp ma3206e ewl+t 9 wlp +aq max3206eetc+ 12 tqfn-ep* +aaca selector guide part esd-protected i/o ports max3202eews+t 2 max3202eett-t 2 MAX3203EEWT+t 3 max3203eett-t 3 max3204eebt-t 4 max3204eett-t 4 max3206eebl-t 6 max3206eetc 6 pin configurations appear at end of data sheet. firewire is a registered trademark of apple computer, inc. max3202e max3204e max3206e max3208e protected circuit 0.1 f 0.1 f i/0_ i/0 v cc v cc typical operating circuit downloaded from: http:///
max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics(v cc = +5v 5%, t a = t min to t max , unless otherwise noted. typical values are at v cc = +5v and t a = +25c.) (note 2) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: limits over temperature are guaranteed by design, not production tested. note 3: idealized clamp voltages (l1 = l2 = l3 = 0) (figure 1 ); see the applications information section for more information. note 4: guaranteed by design. not production tested. v cc to gnd ...........................................................-0.3v to +7.0v i/o_ to gnd ................................................-0.3v to (v cc + 0.3v) continuous power dissipation (t a = +70c) 2 2 wlp (derate 11.5mw/c above +70c)...............920mw 3 2 wlp (derate 12.3mw/c above +70c)...............984mw 3 3 wlp (derate 14.1mw/c above +70c).............1128mw 6-pin tdfn (derate 24.4mw/c above +70c) ..........1951mw 12-pin tqfn (derate 16.9mw/c above +70c) ........1349mw operating temperature range ...........................-40c to +85c storage temperature range .............................-65c to +150c junction temperature .....................................................+150c lead temperature (soldering, 10s) .................................+300c soldering temperature (reflow) .......................................+260c parameter symbol conditions min typ max units supply voltage v cc 0.9 5.5 v supply current i cc 1 100 na diode forward voltage v f i f = 10ma 0.65 0.95 v positive transients v cc + 25 t a = +25c, 15kv human body model,i f = 10a negative transients -25 positive transients v cc + 60 t a = +25c, 8kv contact discharge(iec 61000-4-2), i f = 24a negative transients -60 positive transients v cc + 100 channel clamp voltage(note 3) v c t a = +25c, 15kv air-gap discharge(iec 61000-4-2), i f = 45a negative transients -100 v channel leakage current t a = 0c to +50c (note 4) -1 +1 na channel input capacitance v cc = 5v, bias of v cc /2 5 7 pf esd protection human body model 15 kv iec 61000-4-2contact discharge 8 kv iec 61000-4-2air-gap discharge 15 kv note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . package thermal characteristics (note 1) 4 wlp junction-to-ambient thermal resistance ( ja )...............87c/w 6 wlp junction-to-ambient thermal resistance ( ja )...............84c/w 9 wlp junction-to-ambient thermal resistance ( ja )...............71c/w 6 tdfn junction-to-ambient thermal resistance ( ja )....................42c/w junction-to-case thermal resistance ( jc )...........................9c/w 12 tqfn junction-to-ambient thermal resistance ( ja )....................41c/w junction-to-case thermal resistance ( jc )...........................6c/w downloaded from: http:///
max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces _______________________________________________________________________________________ 3 typical operating characteristics (v cc = +5v, t a = +25c, unless otherwise noted.) pin/bump description pin/bump ma3202e ma3203e ma3204e ma3206e wlp tdfn- ep wlp tdfn- ep wlp tdfn- ep wlp tqfn- ep name function a1, b2 3, 6 a1, a2, b3 1, 2, 4 a1, a2, b2, b3 1, 2, 4, 5 a1, a3, b1, b3, c1, c3 1, 2, 3, 7, 8, 9 i/o_ esd-protected channel a2 4 b1 3 b1 3 a2 5 gnd ground b1 1 a3 6 a3 6 c2 11 v cc power-supply input. bypass v cc to gnd with a 0.1f ceramic capacitor. 2, 5 5 4, 6, 10, 12 n.c. no connection. not internally connected. ep exposed pad. connect to gnd. only for tdfn and tqfn packages. 0.30 0.700.50 1.100.90 1.30 1.50 clamp voltage vs. dc current max3202e toc01 dc current (ma) clamp voltage (v) 30 70 90 50 110 130 150 1 10 100 1000 25 35 45 55 65 75 85 leakage current vs. temperature max3202e toc02 temperature ( c) leakage current (pa) leakage current per channel 2 4 86 10 12 02 13 4 5 input capacitance vs. input voltage max3202e toc03 input voltage (v) input capacitance (pf) v cc = 3.3v v cc = 5.0v downloaded from: http:///
detailed description the max3202e/max3203e/max3204e/max3206e arediode arrays designed to protect sensitive electronics against damage resulting from esd conditions or tran- sient voltages. the low input capacitance makes these devices ideal for high-speed data lines. the max3202e, max3203e, max3204e, and max3206e protect two, three, four, and six channels, respectively. the max3202e/max3203e/max3204e/max3206e are designed to work in conjunction with a devices intrinsic esd protection. the max3202e/max3203e/max3204e/ max3206e limit the excursion of the esd event to below 25v peak voltage when subjected to the human body model waveform. when subjected to the iec 61000-4-2 waveform, the peak voltage is limited to 60v when subjected to contact discharge and 100v when subjected to air-gap discharge. the device that is being protected by the max3202e/max3203e/ max3204e/max3206e must be able to withstand these peak voltages plus any additional voltage generated by the parasitic board. applications information design considerations maximum protection against esd damage results fromproper board layout (see the layout recommendations section and figure 2). a good layout reduces the para-sitic series inductance on the ground line, supply line, and protected signal lines. the max3202e/max3203e/max3204e/max3206e esd diodes clamp the voltage on the protected lines during an esd event and shunt the current to gnd or v cc . in an ideal circuit, the clamping voltage, v c , is defined as the forward voltage drop, v f , of the protection diode plus any supply voltage present on the cathode.for positive esd pulses: v c = v cc + v f for negative esd pulses: v c = -v f in reality, the effect of the parasitic series inductanceon the lines must also be considered (figure 1). for positive esd pulses: for negative esd pulses:where i esd is the esd current pulse. vv l x di dt lx d c fd esd () ( = + ? ? ? ? ? ? + () 2 13 ii dt esd ) ? ? ? ? ? ? ? ? ? ? ? ? vv v lx di dt l cc c fd esd () =+ + ? ? ? ? ? ? + () 1 12 () x di dt esd ? ? ? ? ? ? max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces 4 _______________________________________________________________________________________ l1 protected line l3 d2 ground rail positive supply rail i/o_ d1 l2 figure 1. parasitic series inductance v cc protected line negative esd current pulse path to ground protected circuit gnd d1 i/o_ v c d2 l1 l3 l2 figure 2. layout considerations downloaded from: http:///
max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces _______________________________________________________________________________________ 5 during an esd event, the current pulse rises from zeroto peak value in nanoseconds (figure 3). for example, in a 15kv iec-61000 air-gap discharge esd event, the pulse current rises to approximately 45a in 1ns (di/dt = 45 x 10 9 ). an inductance of only 10nh adds an additional 450v to the clamp voltage. an inductance of10nh represents approximately 0.5in of board trace. regardless of the devices specified diode clamp volt- age, a poor layout with parasitic inductance significantly increases the effective clamp voltage at the protected signal line. a low-esr 0.1f capacitor must be used between v cc and gnd. this bypass capacitor absorbs the chargetransferred by an +8kv iec-61000 contact discharge esd event. ideally, the supply rail (v cc ) would absorb the charge caused by a positive esd strike without changing itsregulated value. in reality, all power supplies have an effective output impedance on their positive rails. if a power supplys effective output impedance is 1 ? , then by using v = i r, the clamping voltage of v c increas- es by the equation v c = i esd x r out . an +8kv iec 61000-4-2 esd event generates a current spike of 24a,so the clamping voltage increases by v c = 24a 1 ? , or v c = 24v. again, a poor layout without proper bypassing increases the clamping voltage. a ceramicchip capacitor mounted as close to the max3202e/ max3203e/max3204e/max3206e v cc pin is the best choice for this application. a bypass capacitor shouldalso be placed as close to the protected device as possible. 15kv esd protection esd protection can be tested in various ways; themax3202e/max3203e/max3204e/max3206e are characterized for protection to the following limits: ? 15kv using the human body model ? 8kv using the contact discharge method speci- fied in iec 61000-4-2 ? 15kv using the iec 61000-4-2 air-gap discharge method esd test conditions esd performance depends on a number of conditions.contact maxim for a reliability report that documents test setup, methodology, and results. human body model figure 4 shows the human body model, and figure 5shows the current waveform it generates when dis- charged into a low impedance. this model consists of a 100pf capacitor charged to the esd voltage of inter- est, which is then discharged into the device through a 1.5k ? resistor. charge-current- limit resistor discharge resistance storagecapacitor c s 100pf r c 1m ? r d 1.5k ? high- voltage dc source device under test figure 4. human body esd test model i p 100% 90% 36.8% t rl time t dl current waveform peak-to-peak ringing(not drawn to scale) i r 10% 0 0 amperes figure 5. human body model current waveform t r = 0.7ns to 1ns 30ns 60ns t 100% 90%10% i peak i figure 3. iec 61000-4-2 esd generator current waveform downloaded from: http:///
max3202e/max3203e/max3204e/max3206e iec 61000-4-2 the iec 61000-4-2 standard covers esd testing andperformance of finished equipment. the max3202e/ max3203e/max3204e/max3206e help users design equipment that meets level 4 of iec 61000-4-2. the main difference between tests done using the human body model and iec 61000-4-2 is higher peak current in iec 61000-4-2. because series resistance is lower in the iec 61000-4-2 esd test model (figure 6) the esd-withstand voltage measured to this standard is generally lower than that measured using the human body model. figure 3 shows the current waveform for the 8kv iec 61000-4-2 level 4 esd contact discharge test. the air-gap discharge test involves approaching thedevice with a charged probe. the contact discharge method connects the probe to the device before the probe is energized. layout recommendations proper circuit-board layout is critical to suppress esd-induced line transients. the max3202e/max3203e/ max3204e/max3206e clamp to 100v; however, with improper layout, the voltage spike at the device is much higher. a lead inductance of 10nh with a 45a current spike at a dv/dt of 1ns results in an addition- al 450v spike on the protected line. it is essential that the layout of the pc board follows these guidelines: 1) minimize trace length between the connector or input terminal, i/o_, and the protected signal line. 2) use separate planes for power and ground to reduce parasitic inductance and to reduce the impedance tothe power rails for shunted esd current. 3) ensure short esd transient return paths to gnd and v cc . 4) minimize conductive power and ground loops. 5) do not place critical signals near the edge of the pc board. 6) bypass v cc to gnd with a low-esr ceramic capac- itor as close to v cc as possible. 7) bypass the supply of the protected device to gnd with a low-esr ceramic capacitor as close to thesupply pin as possible. low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces 6 _______________________________________________________________________________________ charge-current- limit resistor discharge resistance storagecapacitor c s 150pf r c 50 ? to 100 ? r d 330 ? high- voltage dc source device under test figure 6. iec 61000-4-2 esd test model downloaded from: http:///
max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces _______________________________________________________________________________________ 7 table 1. reliability test data test conditions duration failures per sample size temperature cycle -35c to +85c, -40c to +100c 150 cycles, 900 cycles 0/10, 0/200 operating life t a = +70c 240hr 0/10 moisture resistance -20c to +60c, 90% rh 240hr 0/10 low-temperature storage -20c 240hr 0/10 low-temperature operational -10c 24hr 0/10 solderability 8hr steam age 0/15 esd 2000v, human body model 0/5 high-temperature operating life t j = +150c 168hr 0/45 max3202e v cc gnd i/o1 i/o2 max3203e v cc gnd i/o1 i/o3 i/o2 max3204e v cc gnd i/o1 i/o2 i/o3 i/o4 max3206e v cc gnd i/o1 i/o2 i/o5 i/o6 i/o3 i/o4 functional diagrams chip information process: bicmos downloaded from: http:///
max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces 8 _______________________________________________________________________________________ 12 n.c. 11 v cc 10 n.c. 45 gnd 6 n.c. 12 i/02 3 98 7 i/03 i/06i/05 i/04 max3206e i/01 n.c. tqfn wlp a2 a3 i/o4 a1 i/o3i/o2 i/o1 gnd b1 b3 i/o5 c1 c2 c3 i/o6 v cc max3204e wlp a2 a3 a1 i/o2 i/o3 v cc i/o4 gnd i/o1 b1 b2 b3 max3203e wlp a2 a3 a1 i/o2 i/o3 v cc gnd i/o1 b1 b3 max3202e wlp a2 a1 i/o1 gnd top view (bumps on bottom) v cc i/o2 b1 b2 max3206e 12 i/02 3 65 4 gnd v cc i/04i/03 i/01 tdfn max3204e 1 + + 2 i/02 3 65 4 gnd v cc n.c.i/03 i/01 tdfn max3203e 12 n.c. 3 65 4 i/01 i/02n.c. gnd v cc tdfn ++ max3202e ep ep = exposed paddle. connect to gnd. ep ep ep pin configurations package type package code outline no. land pattern no. 4 wlp w41a1+2 21-0455 refer to application note 1891 6 wlp w61c1+2 21-0463 refer to application note 1891 9 wlp w91b1+5 21-0067 refer to application note 1891 6 tdfn-ep t633+2 21-0137 90-0058 12 tqfn-ep t1244+4 21-0139 90-0068 package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a "+", "#", or "-" in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per - tains to the package regardless of rohs status. downloaded from: http:///
max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 _____________________ 9 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 3 12/07 added 3202eews+t tdfn and tqfn packages, updated package information 1, 2, 3, 4, 6, 8, 12C15 4 12/09 corrected part numbers and pin packages in the ordering information table, absolute maimum ratings , selector guide , pin description , and pin configurations . 1C3, 8C15 5 6/11 updated to show available packages as wlp, not ucsp 1, 2, 3, 6, 8 downloaded from: http:///
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